A page mode nonvolatile memory device includes a counter for controlling the addressing of memory locations in the selected page. The address counter starts from the value that is input thereto by the user during a specific command, and as illustrated in the data path flow scheme of FIG. 1, during read operations the value assumed by the address counter selects the memory location from which data is output. This is while during a program operation the value assumed by the address counter selects the memory location where data will be written.
The address counter plays an important role, and represents a critical component of the device. To better illustrate the technical problems to be addressed, a brief review of the manner in which the address counter functions during a read sequence and a program sequence follows.
Referring to the read sequence depicted in FIG. 2, the following are issued to the memory device in order to enter a read mode: a read command (00h), four address cycles (for the example taken into consideration) and a read confirm command (30h).
The internal address counter is initialized by the issuance of the four address cycles, and after this busy state the internal address counter is incremented at every toggling of the external read enable signal REN.
During each address latching cycle ALE, the internal address counter loads input data I/O into the correct position according to the number of the ALE cycle. When the read-confirm command (30h) is issued, the memory device enters a busy state. The memory cell array is accessed and information stored in the page selected by the row address is read and stored into a data register commonly referred to as page buffer.
After this busy state has ended, the external user will toggle the REN read enable command for outputting data read from the page buffer. Data is accessed on a byte or word base such that for any new RE toggling the column address counter will be incremented to select consecutive data stored in the selected page.
Referring to FIG. 3, the following are issued to the memory device in order to enter a program mode: the program command (80h) followed by four address input cycles (for the considered sample case) are issued to the memory device, serial data is loaded in the page buffer, and the program-confirm command (10h).
The internal address counter is initialized by the four address cycles, and subsequently, the counter is incremented at every toggling of the write enable signal WEN during the data cycles. During each ALE cycle, the internal address counter controls the loading of input address bits in the correct positions, according to the number of the ALE cycle.
When the last address cycle is issued, the row address (A27-A12) is frozen while the column address (A11-A0) is incremented at every toggling of the WEN signal during the data cycles in order to load input data in the page buffer in a consecutive mode. An elementary cell of an internal address counter as typically realized for implementing the above described algorithms for read and program operations is shown in FIG. 4.
The external command LOADADD is applied on a pad of the memory device. The ADD signal is cleared when RESET_ADD is high, or briefly H. At the rising edge of the signal address counter CK_ADD, which is internally generated by the input logic circuitry of the counting flip flop (F/F) of the elementary cell or module of the address counter, latches an ADD value which is either: 1) LOADADD, when ENLOAD is H, or 2) (CARRY xor ADD) when ENCOUNT is H and ENLOAD is L.
In all other cases, the ADD value maintains the logical value previously set in the flip flop F/F. ADD represents a Counted Address Value (all ADD values constitute a first internal address bus).
ADD_A is a second Internal address bus that is generated from the ADD values of the first internal address bus to implement a pipeline arrangement for internal simultaneous multiple data transfers.
ENLOAD is high when the memory device loads PAD data as address values during the ALE cycles. If ENLOAD is high, CK_ADD is logically equal to WEN (CLK_SEL=00) and the ADD value is latched according to its PAD value.
After the busy state triggered by a read command sequence has ended, the user reads data from the page buffer by toggling REN. In this case, CK_ADD is logically equal to REN (CLK_SEL01), and the internal column counter value (ADD) is incremented by every new pulse of the REN signal.
Erase Verify is performed to verify whether all cells of a selected block have been erased. To check this condition, an internal algorithm is executed, which downloads cell information in the page buffer and checks whether the data stored in the page buffer data are all 1 on a byte-by-byte bases. For this purpose, column addresses are scanned from beginning to end. During Erase Verify, CK_ADD is equal to Erase_verify_ck (CLK_SEL=10) that is generated during the execution of the erase verify algorithm, and the ADD value is incremented at every new Erase_verify_ck pulse.
During execution of data cycles, the address counter needs to be incremented by WEN. Therefore, CK_ADD is equal to WEN_1CK (CLK_SEL=11) and the internal address counter value ADD is incremented at every WEN toggling. WEN_1CK is a signal whose function is to skip address counter increments during the first data cycle. The reason why such a WEN_1CK signal is used during data cycle is that when loading program data into the page buffer, the first data is to be loaded at the address set during the ALE cycle. Therefore, it is necessary to skip incrementing the address counter during the first WEN pulse of data cycle. Of course, the address counter value ADD is incremented by WEN_1CK starting from the WEN pulse of the second data cycle.
To get a sufficient timing margin for loading data from I/O in the page buffer (or for transferring data from the page buffer to I/O pads), a parallel processing scheme of data transfer is adopted. This is generally referred to as pipelining. FIG. 5 illustrates an example of a pipeline for a read operation.
The example pipeline is for the case of transferring two data in parallel. Therefore, two internal address buses, and two internal data buses are implemented. As described in the previous section, the counted address that is the ADD values stored in the gain or counting flip-flops F/F, that compose the Address Counter in FIG. 4, is the address counter information that forms a first internal address bus (ADD). Another or second internal address bus (ADD-A) is generated by using an adder according to the circuit diagram of FIG. 4 relative to an elementary (or module) of the Address Counter.
In the shown pipeline, whenever the counted address ADD changes, the internal address buses BUS0,1[n:1] also changes. Because there is no bit[0] in the internal address bus BUS1, the latter is updated every other RE pulse. The internal address bus BUS represents the adder result (ADD-A) of the counted address (ADD). This fact implies the occurrence of glitches on the internal address buses BUS0,1 during the portion indicated by the symbol (*) in FIG. 5 (i.e., the falling edge of RE) because of different timing delays in adding the result of a counted address for each bit of the internal address bus bit.
The values of BUS0,1 during the (*) portion of RE in FIG. 5 is unstable because they are changing during such an interval of time. Therefore, they are considered as unknown. On the other hand, these are as other internal address buses are directly connected to the page buffer and to the redundancy block. Therefore, whenever the buses BUS0,1 have glitches, redundancy will be evaluated for changing address values. Moreover, the addressing of the page buffer will also suffer instabilities. The more the duration of these instabilities (i.e., the * portion of RE in FIG. 5) is reduced, the more stable the operation of the page buffer and of the redundancy block will be.
Typically, in the case of a NAND Flash of small page size organization, the specifications require the user to issue a pointer (50h) to access a spare area before performing a read operation or a program operation. Therefore, it is known whether the user is going to access spare area or not before the input of an address.
In case of a small page organization of the memory, the spare area of each page is generally 16 bytes or 8 words. Therefore, when the external user inputs an address through a certain number of ALE cycles to access the spare area, only addresses (or more precisely the address bits) [3:0] (also indicated thereinafter with the short-hand notation A[3:0]) of the column address are available. Other address bits A[7:4] are discarded regardless of the users full address that has been input.
From the point of view of the address counter design, it is necessary to fix the address bits A[7:4] either to a low or high state to ensure correct operation of the counter. In a memory with a small page organization, this is possible because of the above described pointer requisite. In contrast, in case of a large page organization of the memory device, there is no pointer command for accessing the spare area of the memory device, and to do so the user needs to input the address bit All set to a high logic value (X8 mode).
Commonly, in case of a large page organization, the spare area on each page is 64 bytes or 32 words. When the user, through the sequence of ALE cycles, inputs an address in the spare area, only the address bits [5:0] among the column address bits are available. The other address bits[10:6] are to be discarded regardless (X8 mode).
Referring to FIG. 7, there is no chance to set A[10:6] to a low logic value because the information A11 that indicates that the access is to the spare area comes after the address bits A[10:6] have been input. Therefore, the address bits A[10:6] will be different according to the user's input, and because of this the design of the internal counter is generally more complicated to handle this situation.